Power consumption has become a critical concern in both high performance andportable applications. Methods for power reduction based on the application ofadiabatic techniques to CMOS circuits have recently come under renewedinvestigation. In thermodynamics, an adiabatic energy transfer through adissipative medium is one in which losses are made arbitrarily small by causingthe transfer to occur sufficiently slowly. In this work adiabatic technique isused for reduction of average power dissipation. Simulation of 6T SRAM cell hasbeen done for 180nm CMOS technology. It shows that average power dissipation isreduced up to 75% using adiabatic technique and also shows the effect on staticnoise margin.
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